Electrically erasable and programmable non-volatile memory devices include serial access memories and parallel access memories. Certain serial access memories have a block of memory cells that are accessible only once in a write mode. These devices are memories that are programmable only once. This block of memory cells generally contains information, such as manufacturing references registered by the manufacturer of an electronic system incorporating the memory so that the component can be traced. These references could be the reference of the system, the manufacturing batch number, the date of manufacture, etc.
This block of memory cells is generally a group of cells of the memory array itself. More particularly, the block of memory cells is a row of cells of the memory array that is organized in a matrix of rows and columns. This row of memory cells is conventionally called an OTP row, or a one-time programmable row. The memory is then said to provide an OTP function. Since the memory cells of the OTP row have the same structure as those of the rest of the memory array, they are also accessible by an appropriate address. A particular bit of the memory, called an OTP bit, contains either a logic 0 value or a logic 1 value when the OTP row is blank. The OTP row is blank if it has not yet been programmed. If the OTP row is programmed, it has the complementary logic value. The OTP bit is generally a special bit of the OTP row itself. The memory has means to permit or not permit writing in the OTP row, depending on the value of this bit. These means naturally include means to read the OTP bit.
However, since the OTP bit is an unspecified bit of the memory array, it is subject to the same risks of deterioration as the other cells of the memory array. This type of deterioration is caused by the application of high voltages needed to program and erase the cells of the memory array. It is important that the OTP bit keep its programmed value once it is programmed to indicate that the OTP row is no longer blank. Failing to do so results in a risk that the OTP row will be erased by another write operation (intentional or unintentional), if the value of the OTP bit has not been accurately read.
The invention seeks to overcome this drawback of the prior art. None of the parallel access memories presently known in the prior art have any OTP function. On the contrary, parallel access memories often have a so-called SDP, or software data protection function, to protect all the memory cells of the memory array against unintentional write operations. Unintentional write operations could cause accidental loss of data.
For parallel access memories, a write operation is possible when a memory chip select input and a read/write input are in a logic 0 state (a third output enable input is in a logic 1 state). The write operation is prompted by the trailing edge of the last of these two inputs, both of which go to a logic 0 state. The logic values present at the data input are then recorded in the memory cell identified by the address corresponding to the logic values present at the address input of the memory chip. These conditions could all occur without being intentionally set up. Such a condition is when there is noise on the electrical lines connected between the above-mentioned inputs of the memory chip. The SDP function makes it possible to avoid this drawback by ensuring that a series of steps prior to a write command are performed at the inputs of the memory chip so that the write operation is possible. For example, the memory has means to prevent any write operation in the memory cells within the memory array. These means are made inadequate by the performance of the above-mentioned series of steps.
For this purpose, the memory comprises a particular bit called an SDP bit. The bit is a logic 0 value if the memory array is write protected and the bit is a complementary logic value if the memory array is not write protected. The value of this bit is read routinely as soon as a write operation is activated in the memory. The time taken to read this bit must be smaller than a certain period of time after which a memory write cycle is activated to perform a write operation. If the value of the SDP bit indicates that the memory is write protected, then means must be provided to prevent this write cycle from being carried out. Means of this kind generally act to inhibit the operation of a voltage booster circuit delivering the high voltages needed for writing in the memory cell.
For an increased reading speed, the SDP bit is generally a supplementary bit of the memory, i.e., it does not form part of the memory array. The SDP bit is write-accessible by a special procedure whose complexity is sufficient to prevent any unintentional programming or erasure of this bit. The SDP function does not have the same value for the serial access memories, where an unintentional write operation is practically impossible. This is due to the fact that for any operation in the memory, the serial input of the memory must be provided with a sequence of signals according to a specific protocol.